Venkata Sreekanth Balijabudda – SRM University AP, Andhra Pradesh

Hardware Security (Physical Unclonable Functions)
Cryptography (Implementations of Cryptographic Algorithms) and Cryptanalysis (Side-channel security)
Machine Learning and Digital VLSI design

2017 to '19– Senior Research Fellow– IIT Kharagpur, West Bengal
2016 to '17 – Assistant Professor–Sreenidhi Institute of Science and Technology, Hyderabad

Design, Automated Implementation and Analysis of High-Quality Physically Unclonable Functions on Field Programmable Gate Arrays: Intel and AMD FPGAs
Arbiter PUFs, Ring-Oscillator PUFs, Butterfly PUFs and other emerging PUF technologies for Device identification and Authentication.
Implementation of Cryptographic algorithms using robust and efficient methods (to prevent Side-channel leakage)

Journals

B.V. Sreekanth, I. Chakrabarti and, R. S. Chakraborty, “Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs”, 33rd Asian Test Symposium (ATS), 2024.
B.V. Sreekanth, K. Acharya, R. S. Chakraborty, and I. Chakrabarti, “Theoretical Enumeration of Deployable Single-output Strong PUF Instances based on Uniformity and Uniqueness Constraints”, ICISS 2023, Springer Lecture Notes in Computer Science, Volume 14424.
B.V. Sreekanth, D. Thapar, P. Santikellur, R. S. Chakraborty, and I. Chakrabarti, “Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF”, 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2019, pp. 1-6.
Co-inventor, "Trust Establishment of Program Binary on Field Programmable Gate Array using Physically Unclonable Functions”, Patent Application No. 202431037356, Intellectual Property India, May 2024.
Co-inventor, “Untrusted Hardware Module Identification and Reporting for Secure System Implementation on Field Programmable Gate Array Platform”, Patent Published, Intellectual Property India, January 2024.